Traditionally, automated printed circuit board testing involved a functional test wherein input signals were provided to the external inputs of a printed circuit board (PCB) and output signals were observed from the external outputs of the PCB. Also known as "edge-connector functional testing", this type of testing can become very complicated for complex circuitry and can provide only limited diagnostics. Accordingly, modern testing has increasingly supplemented and even replaced this traditional functional test with the efficient, flexible in-circuit test.
In-circuit test is a type of functional circuit test wherein the performance of each digital integrated circuit (IC) on a PCB is independently tested as an independent, functional unit. In order to accomplish this, a tester must apply input signals directly to the inputs of a DUT (device under test) and must access the outputs of the DUT to observe the output response. Each digital IC can then be tested as if it were electrically isolated from the circuit. This allows the in-circuit test to provide excellent diagnostics.
Further, because the devices are independently tested, tests for many common digital IC's can be programmed once, in advance, stored in a library, and then called upon when needed. This greatly simplifies test generation since this pre-programmed test can be used over and over again.
The nodal access required for in-circuit test is achieved using a "bed-of-nails" fixture. The "bed-of-nails" includes a plurality of spring-loaded conductive probes that make ohmic contact directly with the device I/O (input/output) pins from pads or traces on the surface of the PCB. To accomplish this, each node requiring test access must be available at the surface of the PCB and must have sufficient dimensions to allow an individual test probe to make physical (i.e., ohmic) contact with it. If physical contact is not possible, then in-circuit testing may be frustrated.
Lack of test access is precisely the problem that faces test engineers today. Component miniaturization and increasing densities of electronic circuits have vastly reduced node accessibility such that test signal acquisition is becoming increasingly difficult. As designers implement high density components on ultra fine pitch, multi-layer PCB's, many conductors are either not accessible or are too small to be contacted by conventional probing techniques.
For example, the traditional medium scale integration (MSI) chip has given way to the large scale integration (LSI) chip and the very large scale integration (VLSI) chip. The conventional dual-in-line package for these chips has been supplemented by hybrid packages (i.e., bare silicon chips mounted on a common ceramic or silicon substrate), TAB (Tape Automated Bonding), and surface mount. Most recently, state of the art technologies are pushing integration well beyond VLSI. The resultant increase in operational clock speeds (e.g., 10.sup.8 Hz and beyond) has resulted in complex new packaging problems, which have in turn led to development of multichip modules (MCM's).
The MCM is a hybrid assembly which includes a plurality of silicon dies mounted on a common substrate. The same process which is used to form the interconnect system on the chip may be used to form the chip-to-chip interconnect on the substrate. The MCM allows more chips to be brought closer together to accommodate greater I/O rates and greater signal processing speeds. This is accomplished by using fine line and multi-layer interconnection features fabricated through thin film microlithographic techniques.
These state-of-the-art technologies have increased packaging densities at the cost of test accessibility. Design engineers can no longer guarantee the test engineers the node accessibility which they require. Many nodes are trapped on inner layers of a multi-layer PCB. Even if a node is present as an I/O pin of an IC, the fine-pitch geometries of the IC may prohibit probing with the contact-type probes.
These problems are forcing the test engineer to abandon the powerful in-circuit test and return to the more complicated edge-connector functional test. Even edge-connector functional testing frequently requires some degree of internal node access, however, if component-level diagnostics are to be obtained. For example, if an edge-connector test indicates a faulty PCB, it is frequently desirable to "backtrace" through the circuit from the failing output to find the source of the problem. Doing so requires access to outputs available only at internal nodes. Thus, while a return to edge-connector functional testing may alleviate the access problem, it by no means eliminates it.
Additionally, backtracing is frequently performed manually. This requires an operator to hold a probe in physical contact with a pad or other test point. Today's fine pitch geometries make this impractical. TAB devices, for example, frequently have leads on 10 mil (i.e., 10 thousandths of an inch) centers, or closer. At these dimensions, it becomes difficult to identify the leads, much less to probe them.
An additional problem caused by contact-type probing is that the physical force required to make contact may actually close an open-circuit (e.g., close a "cold" solder joint). This can make a problem connection difficult to locate.
Yet another problem which occurs with these conventional probing techniques is that of circuit loading. The load imposed on the circuit by the probe can corrupt the signal being sensed such that the test is invalidated. For example, a capacitive load as small as 1.0 pF may be enough to distrupt some high-frequency circuits.
A method of non-contact test signal acquisition has been suggested in G. Ettinger, et al., "Noncontact Test Signal Acquisition,"Microprocessors and Microsystems, Vol. 6, No. 2, March 1982, pp. 69-71. Ettinger, et al., teach that a digital signal may be detected by capacitive coupling. For detection from a signal carrying source wire, a pickup wire is twisted around the source wire, or a spring clip is clamped around the source wire (e.g., for a distance of 7 mm). For detection from a PCB, a planar capacitive contact is secured to the board above the trace (e.g., 1.5 mm wide traces with 5 mm spacing). Each pickup lead is connected to a saturating receiver, the gate of a field effect transistor (FET), or a CMOS logic gate for signal detection/amplification. This method is claimed to be capable of sensing digital signals over the frequency range of 10 Khz to 10 Mhz.
Unfortunately, the Ettinger et al. teachings are not applicable to solve modern test problems. First, Ettinger et al. teach pickup lead (i.e., probe) sizes which are much too large for use with modern circuits. In order to probe today's ultra fine trace geometries, it is necessary to have an ultra fine probe tip with similar dimensions (e.g., with a diameter on the order of 4 to 10 mils). Traditionally, however, this small size has been considered incapable of producing sufficient capacitive coupling for signal acquisition.
This is because the signal will be attenuated by the proportion of the coupling capacitance to the sum of the input capacitance of the pickup circuit and the coupling capacitance. The coupling capacitance is proportional to the pickup lead (i.e., capacitor plate) surface area which is in proximity to the source wire or trace. Thus, for a fixed input capacitance, the smaller the probe size, the weaker the capacitively sensed signal will be. If the probe size is too small, then the signal will be attenuated beyond that which can be successfully discriminated from the electrical noise of the amplifier/pickup circuit. For example, the sizes of the Ettinger et al. pickup leads are claimed to yield coupling capacitances on the order of 1 pF to 33 pF, while an ultra fine probe tip might yield coupling capacitance on the order or 10 fF (i.e., 10 femtofarads or 0.01 pF). Thus, an ultra fine probe tip would produce a sensed signal at least 100 times smaller in magnitude than the pickup leads of Ettinger et al. The detection/amplification circuits used by Ettinger et al. will not function with input signals this small. Further, the large coupling capacitances taught in Ettinger et al. would produce unacceptable loading on many high-frequency circuits.
These limitations have heretofore prevented development of a commercially practical capacitive probe for test signal acquisition. Seeing little promise in capacitive sensing, the industry has turned to investigation of other technologies for a solution to its test problems.
For example, one method uses a plasma to form a conductive pathway between a trace and a sense electrode. The plasma is created by exciting the sense electrode with a laser. This method is discussed briefly in "Technique eases probing on dense PWBs," by Ashok Bindra, Electronic Engineering Times, Sep. 23, 1991, p. 110.
Another method places a crystal in proximity to the signal carrying conductor. The electric field from the conductor causes changes in the optical properties of the crystal which can be sensed using a laser. This phenomena is known as the Pockels Effect. See Tremblay, G., Meyrueix, P., and Peuzin, I., "Optical Testing of Printed Circuit Boards," Proceedings of the 1988 International Test Conference, pp. 695-699; and Poulsen, P.D., "Electro-optical techniques for non-contact circuit probing," Proceedings of the Society of Photo-Optical Instrumentation Engineers, vol. 153, 1978, pp. 33-39.
These and other exotic methods which are under development have not reached commercial availability due to a variety of technologic and economic obstacles which remain as yet unresolved.